System on Chip (SoC) type integrated circuits typically include a digital circuit that operates in response to a clock signal. The evolution of SoC digital circuit designs requires increasing the frequency of the clock signal. However, as the operating frequency of the clock signal increases, the electromagnetic interference (EMI) also increases. This EMI can be a significant concern, especially in consumer electronics, microprocessor-based systems and data transmission circuits. Reduction of EMI is therefore a critical design feature.
There are a number of known EMI reduction schemes including: the use of a shielding box, skew-rate control circuits and spread spectrum clock generation. Of these options, spread spectrum clock generation is an attractive solution because of its lower hardware cost. As a result, the use of spread spectrum clock generation circuit is a common component of many SoC designs.
Reference is made to FIG. 1 showing a conventional configuration for a spread spectrum clock generator circuit 10 based on a phase-lock-loop (PLL) implementation. The circuit 10 receives a reference frequency signal fref that is fed to a first input of a phase difference detector (PDD) 12. A second input of the phase difference detector 12 receives a feedback frequency signal ffb. The phase difference detector 12 determines a difference in phase between the reference frequency signal fref and the feedback frequency signal ffb. The output of the phase difference detector 12 drives a charge pump (CP) circuit 14 which generates a voltage signal indicative of the determined difference in phase. That voltage signal is then filtered by a low pass filter (LPF) 16 to generate a control signal. A control input of a voltage controlled oscillator (VCO) 18 receives the control signal and generates an output clock signal fout. A divider circuit (/N) 20 divides the output clock signal fout by N to generate the feedback frequency signal ffb. The loop circuit accordingly operates to cause the phase of the output clock signal to lock to the phase of the reference frequency signal fref, wherein a frequency of the output clock signal is an integer multiple (N) of the reference frequency signal fref. To implement spread spectrum control over the output clock signal, the divider value N is modulated by a sigma-delta (ΣΔ) modulator circuit 22. The designation of the modulation profile is provided through an input signal to the sigma-delta modulator circuit 22 that may, for example, have a triangular wave profile. The amplitude and frequency of the modulation profile may be controlled.
FIG. 2 shows a conventional configuration for a spread spectrum clock generator circuit 30 based on a frequency-lock-loop (FLL) implementation. A count difference (CD) circuit 32 receives a reference count Cref at a first input and a feedback count Cfb at a second input. The count difference circuit 32 is a digital circuit that operates to determine a difference in the received count values. That difference value is then filtered by a digital low pass filter (LPF) 34 to generate a digital control signal. A digital-to-analog converter (DAC) circuit 36 converts the digital control signal to an analog control signal. A control input of a current controlled oscillator (CCO) 38 receives the analog control signal and generates an output clock signal fout. A cycle counter circuit (CCC) 40 receives the output clock signal fout and a reference frequency signal fref. The cycle counter circuit 40 operates to count a number of cycles in the output clock signal fout which occur for each single cycle of the reference frequency signal fref. That count is the feedback count Cfb. The loop circuit accordingly operates to cause a frequency of the output clock signal to lock to an integer multiple of a frequency of the reference frequency signal fref, wherein the integer multiple is designated by the value of the reference count Cref. To implement spread spectrum control, the reference count Cref is a count with a value of N modulated by a sigma-delta (ΣΔ) modulator circuit 42. The designation of the modulation profile is provided through an input signal to the sigma-delta modulator circuit 42 that may, for example, have a triangular wave profile. The amplitude and frequency of the modulation profile may be controlled.
The triangular wave profile for the input signal to the sigma-delta modulator circuit 22 or 42 provides for a near optimum spreading of the spectrum so as to mitigate EMI effects. The fractional resolution required by spread spectrum clock generator modulation is achieved through the sigma-delta modulator circuit 22 or 42. One problem with this approach is that high frequency modulation cannot be achieved. The spread spectrum clock generator modulation must be at least three times less than the bandwidth of the system circuit 10 or 30 in order to pass at least the third harmonic of the fundamental frequency of the triangular wave. The bandwidth of the system circuit 10 or 30 is mainly a function of the reference frequency signal fref. For example, the maximum bandwidth possible for the PLL implementation is about one-eighth of the reference frequency. If taking into account process, voltage, temperature (PVT) variation of the bandwidth, the ratio is reduced to about one-twenty-fourth. Now further allowing for three harmonics of the triangular wave, the maximum frequency of the spread spectrum clock generator profile would be one-seventy-second.
New SoC designs and new standards will require modulation frequencies up to or above 2 MHz with reference frequencies as low as 32 kHz. The solutions of FIGS. 1 and 2 are not usable. A need accordingly exists for a spread spectrum clock generator having a high modulation frequency. Preferably, operation of the generator is not dependent on reference frequency. Still further, the modulation depth and modulation frequency for the generated spread spectrum clock should be programmable and PVT tolerant.